DRAM integrated circuit arrays have existed for more than twenty five years and have evolved from the earliest one kilobit (Kb) generation to the recent 256 megabit (Mb) generation. This dramatic increase in storage capacity has been achieved through advances in semiconductor fabrication technology and circuit design technology. The tremendous advances in these two technologies have also achieved higher and higher levels of integration that permit dramatic reductions in memory array size and cost, as well as increased process yield.
A DRAM memory cell typically comprises, as basic components, an access transistor (switch) and a capacitor for storing a binary data bit in the form of a charge. Typically, a charge of one polarity is stored on the capacitor to represent a binary ONE, and a stored charge of the opposite polarity represents a binary ZERO. The basic drawback of a DRAM is that the charge on the capacitor eventually leaks away and therefore provisions must be made to "refresh" the capacitor charge or else the data bit stored by the memory cell is lost.
The memory cell of a conventional SRAM, on the other hand, comprises, as basic components, an access transistor or transistors and a memory element in the form of two or more integrated circuit devices interconnected to function as a bistable latch. An example of such a bistable latch is cross-coupled inverters. Bistable latches do not need to be "refreshed", as in the case of DRAM memory cells, and will reliably store a data bit indefinitely as long as they continue to receive supply voltage.
Efforts continue to identify other forms of memory elements for use in SRAMs. Recent studies have focused on resistive materials that can be programmed to exhibit either high or low stable ohmic states. A programmable resistance element of such material could be programmed (set) to a high resistive state to store, for example, a ONE data bit or programmed to a low resistive state to store a ZERO data bit. The stored data bit could then be retrieved by detecting the magnitude of a readout current switched through the resistive memory element by an access device, thus indicating the stable resistance state it had previously been programmed to.
One particularly promising programmable, bistable resistive material is chalcogenide, such as the alloy system including Ge:Sb:Te disclosed in Ovshinsky et al., U.S. Pat. No. 5,414,271, the disclosure of which is incorporated herein by reference. A memory element comprised of a chalcogenide material can be programmed to a stable high resistive state by passing a narrow, high amplitude current pulse through it. A lower amplitude current pulse of longer duration programs a chalcogenide memory element to a stable, low resistive state. A chalcogenide memory element is simply written over by the appropriate current pulse to reprogram it, and thus does not need to be erased. Moreover, a memory element of chalcogenide material is nonvolatile, in that it need not be connected to a power supply to retain its programmed high or low resistive state.
However, suitable circuitry for reading and writing data from an array of chalcogenide resistance elements has not yet been fully developed. Accordingly, in order to realize a functional chalcogenide memory, appropriate read circuitry is required to nondestructively sense data stored in the array, and write circuitry is required to accurately write data into the array.
Further, spurious or noise currents may flow in conductive lines within the memory array. These currents can then flow through the chalcogenide memory elements and program erroneous bits into the array.